This application claims the priority of Korean Patent Application No. 2003-45410, filed on Jul. 4, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a stack type semiconductor package in which multiple semiconductor chips are stacked.
2. Description of the Related Art
As the size of electronic products becomes smaller, a semiconductor device mounted on the electronic products is also becoming highly integrated and becoming smaller in size. Therefore, research on reducing size and thickness of a semiconductor package has been actively conducted in order to mount more semiconductor chips on a substrate of limited size. As a result of this active research, a chip scale package (CSP) has been developed.
The CSP reduces the area occupied by the semiconductor device by manufacturing the size of the semiconductor device almost identical with that of the semiconductor chip inside the package. In addition, the recent development of the CSP is followed by a stack type CSP reducing the occupied area of the semiconductor device by stacking plural semiconductor chips on a single substrate.
FIG. 1 is a drawing illustrating an example of a general stack type chip package.
Considering the size of the chip package, a bonding process is performed using a wire WR in a stack type chip package 100 of FIG. 1. That is, instead of stacking printed circuit boards on semiconductor chips CP1 and CP2, the respective semiconductor chips CP1 and CP2 are stacked and connected to a substrate SBT using the wire WR. An insulation or adhesion material is filled between the substrate and the semiconductor chip CP1, and between the semiconductor chips CP1 and CP2.
If the stack type package 100 of FIG. 1 has the semiconductor chips CP1 and CP2 having an edge pad structure, there is no considerable problem in manufacturing the package. However, if the stack type package 100 has the semiconductor chips CP1 and CP2 including a center pad structure, there are some difficulties in producing the package.
The reason lies in the fact that bonding is carried out in the center of the semiconductor chip in a flat type package structure which uses a single semiconductor chip for the package, whereas in the stack type package, it is performed in the outer perimeter of the semiconductor chip. Thus, in the stack type package, an extra constructing process is needed in order to execute the bonding in the outer perimeter of the semiconductor chip.